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A total of 117 records were found in 0.64 seconds
Low Energy I-Cache for Embedded Processors
CDES, 95-99, 2007
Reducing Memory References for FFT Calculation
CDES, 141-145, 2006
Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor
FPL, 582-585, 2005
Template-driven Emotions Generation in Malay Text-to-Speech: A Preliminary Experiment
CITA, 144-149, 2005
Dynamic Cell Allocation to Input Queues in a Combined I/O Buffered ATM Switch
International Conference on Internet Computing (1), 521-527, 2001
An Analytical Model for Service-Differentiated Active Queue Management Schemes in Packet Switched Networks
International Conference on Internet Computing (1), 458-463, 2001
A New Hierarchical Small-Node Degree Interconnection Network
Applied Informatics, 548-550, 1999
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking
Nonlinear programming - theory and algorithms (2. ed.)
Wiley, ISBN: 978-0-471-55793-7I-XIII, 1-638, 1993
A programmable VLSI array with constant I/O pins
Algorithms and Parallel VLSI Architectures, 205-210, 1991